Although the clock frequency is determined by the system specifications, the usage of DET flip-flops can reduce the clock frequency to half of its original value for the same data throughput. Double Edge Triggered Flip Flops stores data on both the rising edge and falling edge of a clock signal. This paper provides an efficient design and analysis of Serial In Serial Out (SISO), Serial In Parallel Out (SIPO), Parallel In Serial Out (PISO) and Parallel In Parallel Out (PIPO) shift registers using High Performance Double Edge Triggered D-Flip flop (DETFF). International Journal of Engineering Research & Technology (IJERT)ġII Year M.Tech, VLSI Design, Sathyabama University, Chennai.Ģ Asst.Professor, Department of ECE, Sathyabama University, Chennai.ģ Principal, Jeppiaar Institute of Technology, Kunnam, Chennai. 2GHz High Performance Double Edge Triggered D-Flip Flop Based Shift Registers In 32NM CMOS Technology
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |